
// Library name: DOMINO
// Cell name: 2_INPUT_VTL_AND
// View name: schematic
M3 (net5 CLK 0 0) NMOS_VTL w=300n l=50n as=3.15e-14 ad=3.15e-14 ps=510.0n \
        pd=510.0n ld=105n ls=105n m=1
M2 (net9 B net5 0) NMOS_VTL w=270.0n l=50n as=2.835e-14 ad=2.835e-14 \
        ps=480.0n pd=480.0n ld=105n ls=105n m=1
M1 (net13 A net9 0) NMOS_VTL w=270.0n l=50n as=2.835e-14 ad=2.835e-14 \
        ps=480.0n pd=480.0n ld=105n ls=105n m=1
M0 (OUT net13 0 0) NMOS_VTL w=90n l=50n as=9.45e-15 ad=9.45e-15 ps=300n \
        pd=300n ld=105n ls=105n m=1
V0 (vdd! 0) vsource dc=1.1 type=dc
M6 (net13 OUT vdd! vdd!) PMOS_VTL w=90n l=50n as=9.45e-15 ad=9.45e-15 \
        ps=300n pd=300n ld=105n ls=105n m=1
M5 (OUT net13 vdd! vdd!) PMOS_VTL w=180.0n l=50n as=1.89e-14 ad=1.89e-14 \
        ps=390.0n pd=390.0n ld=105n ls=105n m=1
M4 (net13 CLK vdd! vdd!) PMOS_VTL w=180.0n l=50n as=1.89e-14 ad=1.89e-14 \
        ps=390.0n pd=390.0n ld=105n ls=105n m=1
